fpga-trading-systems
Unverified Other strategy on Indices by adilsondias-engineer. BotFinder score 18 out of 100.
Production-grade low-latency FPGA trading system. Features custom VHDL 10GBASE-R PHY, hardware NASDAQ ITCH 5.0 order book, C++ DPDK/XDP kernel bypass, and PCIe DMA acceleration. LL
Source: github
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fpga-trading-systems
Ultra-Low Latency FPGA Trading System & HFT Infrastructure FPGA Trading Systems End-to-end High-Frequency Trading (HFT) infrastructure framework. This repository features a full hardware-software co-design: a custom VHDL 10GBASE-R PHY networking stack running on an FPGA, tightly coupled with an ultra-low latency C++20 kernel bypass subsystem using DPDK and Linux XDP (eBPF). Hardware-accelerated market data processing and order book management for low-latency trading systems. Features custom 10GBASE-R PHY (zero vendor IP), NASDAQ ITCH 5.0 protocol parsing, hardware order book with sub-microsecond latency, and advanced clock domain crossing architecture. --- Flagship Project: Open-Source 10 Gigabit Ethernet The only open-source custom 10GBASE-R Physical Coding Sublayer for trading systems. Implemented IEEE 802.3ae 10GBASE-R from scratch in VHDL (Projects 33-34, 38): - 64B/66B Encoding - Full block coding implementation - Scrambler/Descrambler - Self-synchronizing polynomial (X^58+X^39+1) - Block Lock FSM - Header-based synchronization state machine - GTX Configuration - 10.3125 Gbps tr
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