hft-verilog-generator
Unverified Other strategy on Multi by NaregAmirianMegan. BotFinder score 18 out of 100.
Convert json descriptions of quant algorithms to verilog HDL.
Source: github
BotFinder analysis pending.
hft-verilog-generator
hft-verilog-generator Intro Convert json descriptions of quant algorithms to verilog HDL and backtest the hardware on price time series data. Usage Requirements - icarus verilog compiler - gtkwave - python 3.6 or greater Summary Given a json formatted description of a rule based quantitative algorithm src/generator/genverilog.py generates a verilog module describing the behavior in hardware. Given .csv data and the verilog generated by the previous script src/generator/gentestbench.py generates a raw input hex file and a verilog test bench used to input the data signals to the fpga hardware. When compiled with iverilog the verilog test bench will generate an output file of buy/sell/hold signals over time which can be analyzed by src/analysis/profitanalyzer.py to discover statistics about the algorithm such as total percent profit and average percent profit per trade (buy, sell). File Formats CSV Data: JSON Algo Description: The signals in the json file should match the fields in the .csv that will be used for backtesting. Refrain from using verilog keywords like module, time, begin,
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